Main Power Input Protection and Distribution¶
This section documents the protection and control circuitry for the primary power entry path of the system.
This path covers:
Battery / alternator input → protection stage → MOSFET isolation → downstream regulators (LMR3651) → system 5 V and 3.3 V rails.
It protects the entire board power system, including:
• alternator field drive power path
• LMR3651 regulator input
• 5 V system rail
• 3.3 V rail (derived downstream)
It does NOT protect external sensor inputs. Sensor input protection is implemented separately and documented in another section.
Device Overview¶
Part: TPS48000‑Q1
Package: DGX (VSSOP‑19)
Function:
100 V automotive high‑side driver with protection.
Key features used in this design:
• Reverse polarity tolerance to −65 V
• Programmable overvoltage protection
• Programmable short‑circuit protection
• Fast MOSFET shutdown (~5 µs)
• Integrated charge pump for N‑MOSFET control
Although the device is AEC‑Q100 automotive qualified, it is used here in a marine electrical system. Automotive electrical environments are generally harsher than typical marine systems (load dump, cold crank, large transients), making the device suitable for marine use.
Protection MOSFETs¶
Part: Infineon BSC072N08NS5
Package: TDSON-8 (SuperSO8 5×6 mm)
Quantity: 2, back-to-back configuration
The same device (BSC072N08NS5ATMA1) is used for Q3 in the alternator field drive stage.
| Parameter | Value |
|---|---|
| Drain-Source Voltage (Vds max) | 80 V |
| Rds(on) max @ Vgs = 10 V | 7.2 mΩ |
| Continuous Drain Current (Id) | 47 A |
| Gate Threshold Voltage (Vgs(th)) | 3.8 V |
| Total Gate Charge (Qg) | 29 nC @ 10 V |
| Input Capacitance (Ciss) | 2.1 nF |
| Reverse Transfer Capacitance (Crss / Cgd) | 26 pF |
| Power Dissipation (Pd) | 69 W |
Sources are tied together at the SRC node (TPS48000 pin 13). Gates are tied together at the G_MOSFET node. This arrangement cancels body diodes in both directions, blocks reverse-polarity current, and provides full bidirectional isolation on fault.
Conduction loss at 1 A nominal: I² × 2 × Rds(on) ≈ 14 mW — negligible.
Conduction loss at 15 A SCP threshold: I² × 2 × Rds(on) ≈ 3.2 W — brief exposure before SCP fires.
Gate Drive and Inrush Current Control¶
The TPS48000 drives both FET gates simultaneously through two dedicated pins:
PU (Pin 15) — Pull-Up
High-current gate driver sourcing current from BST toward SRC. Connected to G_MOSFET via R30 (10 Ω, 0603). R30 damps gate-loop ringing at turn-on. For inrush slew rate control, R30 must be increased substantially — see Future Plans.
PD (Pin 14) — Pull-Down
High-current gate driver sinking the gate toward SRC. Connected directly to G_MOSFET with no series resistance. This ensures the gate discharges rapidly (~5 µs) during OVP or SCP fault events, independent of R30.
Bootstrap Capacitor — C5 = 100 nF
Connects BST (pin 12) to SRC (pin 13). The internal charge pump produces approximately 11 V above SRC (V_BST-SRC ≈ 11 V) across the full VIN operating range, maintaining full MOSFET enhancement regardless of battery voltage.
Gate drive timing (current configuration, R30 = 10 Ω):
The PU pin sources up to 1.69 A peak. With R30 = 10 Ω in series and total parallel FET input capacitance Ciss = 2 × 2.1 nF = 4.2 nF, the gate RC time constant is:
τ = R30 × Ciss = 10 Ω × 4.2 nF = 42 ns
Gate turn-on time to full enhancement is approximately 100–200 ns, dominated by the Miller plateau and total gate charge Qg = 2 × 29 nC = 58 nC at the available PU source current. Turn-off through PD (no series resistance) is approximately 5 µs from fault detection to full FET shutdown.
Downstream node dV/dt at turn-on:
During turn-on the MOSFET source follows the gate voltage. With gate slew on the order of 100 ns, VIN_2-60 attempts to slew at approximately:
dV/dt ≈ V_battery / t_turn-on
At 48 V input, dV/dt approaches 480 V/µs at the protected rail. The downstream capacitance (≈ 21 µF total) charges through the trace inductance between the MOSFET stage and the bulk cap node (estimated 8 nH for the 15 mm, 2 mm wide, 1 oz copper trace).
LC tank characteristics:
The trace inductance and downstream bulk capacitance form an underdamped LC tank during fast turn-on events:
| Parameter | Value |
|---|---|
| Trace inductance (L) | ≈ 8 nH |
| Bulk capacitance (C) | ≈ 18.8 µF (4 × 4.7 µF bank) |
| Resonant period | ≈ 2.4 µs |
| Resonant frequency | ≈ 410 kHz |
| Characteristic impedance (Z₀) | ≈ 21 mΩ |
| Damping (Rds(on) + shunt + cap ESR) | ≈ 17 mΩ |
| Damping ratio (ζ) | ≈ 0.4 |
This is an underdamped system. Fast turn-on events excite the LC tank and produce voltage overshoot on the protected rail. Overshoot magnitude depends on how quickly the gate slews relative to the LC tank period.
Operating implication:
With R30 = 10 Ω, gate slew is approximately 100 ns — far faster than the 2.4 µs LC tank period. The tank is fully excited on each turn-on event. The downstream rail sees voltage overshoot proportional to input voltage. See Future Plans for the slew rate control approach.
Charge pump ripple:
The TPS48000 charge pump operates in burst mode to maintain low quiescent current. This produces an approximately 21 Hz ripple of ~1 V peak-to-peak on V_BST-SRC, visible as ripple on the MOSFET gate. The ripple is intrinsic to the chip's low-power design, independent of load and input voltage, and does not affect MOSFET operation since V_GS minimum stays well above the full-enhancement knee.
C45 (DNP)
A capacitor footprint across CS+ and CS− (current sense inputs). Not populated.
EN/UVLO (Pin 1) – Enable / Undervoltage Lockout¶
Thresholds from datasheet:
| Parameter | Value |
|---|---|
| Rising | 1.176–1.287 V |
| Typical | 1.23 V |
| Falling | 1.09–1.184 V |
| Typical | 1.136 V |
Divider network:
R1 = 750 kΩ
R2 = 249 kΩ
Tolerance = 0.1 %
Total resistance:
999 kΩ
Battery turn‑on voltage:
Vbat = Vth × (R1 + R2) / R2
Typical:
1.23 V × (999 kΩ / 249 kΩ)
≈ 4.94 V
Turn‑on voltage range:
| Condition | Battery Voltage |
|---|---|
| Minimum | 4.72 V |
| Typical | 4.94 V |
| Maximum | 5.17 V |
Turn‑off voltage:
Typical ≈ 4.57 V
Purpose:
This divider ensures the controller does not attempt to operate when the input supply is extremely low and guarantees clean startup behavior.
Divider current:
| VIN | Current |
|---|---|
| 12 V | 12 µA |
Overvoltage Protection (OVP)¶
The OV pin detects excessive battery voltage.
Divider network:
R_top = 511 kΩ (0.1 %)
R_bottom = 10.2 kΩ (0.1 %)
Total resistance:
521.2 kΩ
Divider ratio:
Vov = Vin × (10.2k / 521.2k)
≈ 0.01957
OV comparator thresholds:
| Parameter | Voltage |
|---|---|
| Rising | 1.171–1.278 V |
| Typical | 1.225 V |
| Falling | 1.088–1.186 V |
| Typical | 1.138 V |
Resulting battery trip levels:
| Condition | Voltage |
|---|---|
| Minimum trip | 59.8 V |
| Typical trip | 62.6 V |
| Maximum trip | 65.3 V |
Recovery levels:
| Condition | Voltage |
|---|---|
| Earliest re‑enable | 55.6 V |
| Typical re‑enable | 58.2 V |
| Latest re‑enable | 60.6 V |
Divider current:
| VIN | Current |
|---|---|
| 12 V | 23 µA |
| 60 V | 115 µA |
Behavior:
When OV exceeds the rising threshold, the controller pulls PD to SRC, discharging the MOSFET gates and shutting off the pass FETs.
Shutdown propagation delay:
≈ 4.5 µs typical
≈ 5.4 µs max
Short‑Circuit Protection (SCP)¶
Current sensing is performed across a 2 mΩ shunt resistor.
Part used:
HoLLR2010‑1.5W‑2mR‑1%
Important layout requirement:
Because the sense voltage is only ~30 mV at trip, the resistor must be Kelvin sensed with dedicated sense traces to the CS+ and CS− pins. PCB trace resistance can otherwise introduce significant error.
Trip calculation:
RISCP = (I × Rsense − 19 mV) / 2 µA
For 15 A target:
≈ 5.5 kΩ
Selected resistor:
5.6 kΩ
Result:
Trip current ≈ 15.1 A
Sense voltage:
≈ 30.2 mV
Fault Timer¶
Timer capacitor:
CTMR = 1 µF
Trip delay:
t = (C × 1.1 V) / 80 µA
≈ 13.8 ms
Retry interval:
t = 22.7×10⁶ × C
≈ 22.7 s
Timer behavior:
CTMR charges at 80 µA during overcurrent and discharges at 2.5 µA when the fault clears.
Because charge is much faster than discharge (~32:1 ratio), repeated PWM current peaks accumulate toward a trip event.
This configuration acts as a sustained fault detector, not a cycle‑by‑cycle current limiter.
The retry interval (≈ 22.7 s) is long enough that repeated startup events do not create significant thermal stress on the pass FETs.
PWM Interaction¶
PWM frequency ≈ 1200 Hz
PWM period:
≈ 833 µs
Since the SCP delay is 13.8 ms, many PWM cycles occur before a trip decision is made.
Therefore the protection responds to sustained overcurrent, not short PWM spikes.
Note, all of this analysis assumes a squarewave current profile, but in reality it will be smoother. Changing the switching frequency will not meaningfully affect the behavior, just shift the response timeframe slighly.
Transient Protection¶
A SMBJ64CA bidirectional TVS diode is placed across VIN and ground.
Key parameters:
| Parameter | Value |
|---|---|
| Stand‑off voltage | 64 V |
| Breakdown voltage | 71.1–78.6 V |
| Clamp voltage | 103 V @ 5.8 A |
| Peak pulse power | 600 W (10/1000 µs) |
The TVS remains off during normal operation.
It begins conducting only once voltage exceeds roughly 71 V.
The TVS protects the raw, unprotected VIN side — between the battery terminals and the MOSFET stage. It does not clamp the protected downstream rail (VIN_2-60). Protection of the downstream rail against inrush-related overshoot is governed by the MOSFET gate slew rate and the downstream capacitor bank.
The TVS clamp voltage (103 V) is well above the LMR36510 absolute maximum input of 70 V. The raw-side TVS provides no protection to the regulator against inrush-related overshoot — that function is served by the MOSFET gate slew rate.
Downstream Energy Buffer¶
Capacitance between the MOSFET stage and regulator input:
| Capacitor | Quantity |
|---|---|
| 4.7 µF | ×4 |
| 100 nF | ×1 |
| 2.2 µF | ×1 |
| 220 nF | ×1 |
Total ≈ 21 µF
This slows voltage rise during transient events.
Example:
If 20 A surge current enters the node:
dV/dt = I / C
≈ 0.95 V/µs
With a ~5 µs shutdown delay, voltage rises roughly 5 V before isolation occurs.
Physical layout:
The 4 × 4.7 µF and 100 nF capacitors are located at the VIN_2-60 node, approximately 15 mm from the MOSFET stage, connected via a 2 mm wide, 1 oz copper trace. These capacitors are also the local bulk decoupling for the alternator field drive circuit.
The 2.2 µF and 220 nF capacitors are located directly at the LMR36510 VIN pin.
Reverse Polarity Protection¶
Protection is provided by back‑to‑back N‑MOSFETs controlled by the TPS48000.
This arrangement cancels the MOSFET body diodes and blocks current when the battery is connected backwards.
The TPS48000 itself tolerates reverse input voltage to −65 V.
A Schottky diode from GND to VOUT clamps negative excursions at the protected rail.
Lightning‑Induced Transients¶
Nearby lightning strikes can couple large voltage spikes into vessel wiring.
These surges may be positive or negative relative to ground.
Protection layers:
- TVS diode clamps large spikes
- Input capacitors absorb high‑frequency energy
- TPS48000 detects overvoltage
- MOSFETs isolate downstream electronics
The system is not designed to survive a direct lightning strike (obviously), but is intended to tolerate induced surges conducted through long marine wiring as best possible without turning the project into a rabbit hole.
Power Consumption¶
Worst‑case TPS48000 quiescent current used: 55 µA
Battery Present¶
| VIN | EN/UVLO Current | OV Current | TPS48000 IQ | Total |
|---|---|---|---|---|
| 13 V | 13 µA | 25 µA | 55 µA | 93 µA |
| 26 V | 26 µA | 50 µA | 55 µA | 131 µA |
| 52 V | 52 µA | 100 µA | 55 µA | 207 µA |
Total standby dissipation at 52 V:
≈ 10.8 mW
Battery Absent (USB Power)¶
If the battery is physically absent, the TPS48000 front‑end receives no supply and therefore draws zero current from the battery rail.
The TPS2116 power multiplexer then routes USB power to the 5 V system rail.
TPS2116 standby current is only a few microamps and is negligible.
Design Intent¶
This protection system is designed to tolerate:
• alternator load‑dump transients
• long cable inductive spikes
• lightning‑induced surges conducted through vessel wiring
Protection strategy:
- TVS clamps the fastest surge energy on the raw input rail
- Input capacitors absorb high‑frequency spikes
- Gate slew rate on MOSFET turn-on limits inrush current and controls dV/dt on the downstream capacitor bank
- TPS48000 detects faults (OVP, SCP, UVLO)
- MOSFETs disconnect the load
- Downstream capacitance limits further dv/dt rise during the ~5 µs shutdown propagation delay
This layered architecture allows reliable operation in harsh marine environments while protecting the regulator.
Future Plans¶
- 150 V MOSFET upgrade: Replace BSC072N08NS5 (80 V) with Infineon BSC093N15NS5 (150 V, 9.3 mΩ, TDSON-8 drop-in). Provides substantial Vds headroom for transient events on 48 V systems. Minor Rds(on) increase is negligible at operating currents.
- Proper inrush current control (requires PCB respin): Implement TI's R1/R2/C1 gate slew topology per TPS48000 datasheet section 7.3.2. Component values: R30 → 100 kΩ, add R2 = 10 Ω series with C1 in the gate path, add C1 = 150 pF rated ≥ 100 V connected from G_MOSFET to VIN_2-60 (load-side drain). C1 provides Miller feedback that controls MOSFET turn-on speed independently of PU drive strength, producing a controlled millisecond-scale turn-on ramp robust across part variation and temperature. C1 must connect between G_MOSFET and VIN_2-60 — this footprint does not exist on the current PCB. Implementing this topology requires a board respin.
- Conformal coating: See Conformal Coating.