Hardware Versions¶
This page tracks board-level changes between hardware revisions — what changed, why it changed, and what (if anything) it means for units already in service. Newest changes first.
| Version | Status | Timeline | Notes |
|---|---|---|---|
| V1–V8 | Development prototypes | 2024 – early 2026 | Internal design iterations; never shipped. |
| V9 | Current production | First customer shipments Summer 2026 | The board documented throughout this site. |
| V10 | Planned | PCB order Fall 2026; customer deployment Winter 2026–27 | Changes documented below as they are finalized. |
V9 → V10¶
Field-drive bootstrap refresh at low PWM frequencies¶
Applies to: V9 boards in P-type (high-drive) field configuration only. N-type (low-drive) wiring is unaffected.
On V9 the high-side gate driver's bootstrap supply drains through the gate pull-down while the field MOSFET is held on, limiting continuous on-time to about 0.6 ms before the driver's undervoltage lockout briefly refreshes the bootstrap — a ~200 ns self-interruption that then repeats every 120–240 µs for the rest of the on-pulse. At PWM frequencies below about 5 kHz this refresh cycle is active during normal charging. The full circuit analysis (bootstrap budget, discharge time constant, bench measurements) is in Alternator Field Control.
The driver protects itself, the MOSFET stays fully enhanced, and regulation is unaffected — the control loop absorbs the sub-0.2% duty difference. Measured efficiency impact is negligible (tens of millivolts at the field terminal). The only practical downside is acoustic: the refresh cycle modulates the field at an audible 4–8 kHz rate, so a field coil can produce a faint whine at low PWM frequency settings.
On V9: the firmware default field PWM frequency is 400 Hz. Bench A/B testing across 100 Hz – 19 kHz measured no efficiency difference (all deltas within measurement noise), so the frequency choice is about signal cleanliness rather than efficiency: a low default keeps switching edges sparse and away from the regulator's sensor wiring. The full range up to the ESP32 PWM peripheral's ceiling at the 12-bit duty resolution the regulator uses (19.45 kHz) is available in the dashboard. Any setting of 5 kHz or above eliminates the refresh cycle entirely (a 99% on-pulse at 19 kHz is ~52 µs, far below the ~0.6 ms bootstrap limit); at the default and other settings below ~5 kHz the benign refresh behavior shown above is active.
In V10: the gate pull-down (R108) and bootstrap capacitor (C4) change value, extending bootstrap hold-up by more than two orders of magnitude. This removes the constraint altogether — any PWM frequency from 100 Hz up is clean. Component values and bench validation are in Alternator Field Control.
Further revision entries will be added here as hardware evolves.